Date: Mon, 02 Dec 1996 15:12:20 GMT
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<h1>CSE 567: Principles of Digital Systems Design </h1>
<h3>Carl Ebeling, Fall 1996 </h2>
<hr>
<a href="gate-syn.html">Notes on synthesis</a> for homework #3.
<p>
<h3>Cadence online documentation.</h3>
To get to the Cadence online documenation, run "openbook".  You'll
probably have to source the $UW_VLSI_TOOLS/setups/cadence.cshrc file
first.  We use Verilog-XL simulator for all our simulation.  The
documentation you might want to look at are under "HDL
Tools->Verilog-XL Simulation":
<ul>
<LI>Verilog-XL Reference
<LI>Verilog-XL Tutorial 
<LI>Verilog-XL User Guide
</ul>
<P>

<h3>Synopsys online documentation.</h3>
To get to the Synopsys online documentation, run "iview".  You'll
probably have to source the $UW_VLSI_TOOLS/setups/synopsys.cshrc file
first.  The Synopsys documentation of interest includes:
<ul>
<LI>Synthesis:
   <ul>
   <LI>HDL Compiler for Verilog Reference Manual
   <LI>FPGA Compiler Reference Manua
   </ul>
<LI>Tutorials:
   <UL>
   <LI>DesignSource Tutorial for Verilog
   </ul>
</ul>
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<address>
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ebeling@cs.washington.edu
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